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Adaptive Congestion Sensitive Routing Algorithm Based on the Number of Steps in the Networks on Chip

Author Affiliations

  • 1Islamic Azad University, Science and Research Branch, Tabriz, IRAN
  • 2 Islamic Azad University, Qazvin Branch, IRAN
  • 3 Islamic Azad University, Medical Science, Tehran, IRAN

Res. J. Recent Sci., Volume 4, Issue (3), Pages 100-105, March,2 (2015)


Because of Inefficiency of shared bus Networks on chip that is a new architecture has recently attracted much attention of researchers. Recent progress in semiconductor technology forced researchers to design more complete circuit in chips. Although the subject of networks on chip is proposed in this decade, but in the short time since the presentation of this idea, it has been an important issue in computer architecture. The most important factor in networks on chip performance which has directly related to the routing algorithm is reduction in transmit delay, power consumption and switch count. In proposed paper presented an Adaptive congestion Sensitive Routing Algorithm based on the number of steps in networks on chip for mesh topology in order to achieve greater speed and performance, reducing the packet loss and efficient use of switch buffers.


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