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Design of HSDPA System with Turbo Iterative Equalization

Author Affiliations

  • 1 Joginpally B R Engineering college
  • 2 Vivekananda college of engineering for women

Res. J. Recent Sci., Volume 4, Issue (1), Pages 87-93, January,2 (2015)


High Speed Packet data Access (HSPA) has been designed to increase packet data performance, higher data service and lowest bit rates .HSDPA receiver was designed in terms of computation requirement and power consumption from the Turbo Decoder by effectively deploying pipelining or parallelism. The parallelism on the Architecture is proposed to achieve the high-throughput demand for turbo decoder for Fourth Generation (4G) wireless communication systems. The Multiple soft-in/soft-out (SISO) decoders are used to achieve parallel architecture. The soft-output decisions are performed through an iterative process and achieved by soft-input soft-output (SISO) multi-code detector and a SISO turbo decoder. The parallel architecture leads to conflicts during memory accesses. A complete memory conflict analysis for different interleaver patterns has been performed and shows the effect of using different decoding configurations on the memory conflicts for different standards. This can be reduced significantly from the conflict. The iteration is based on the priority information, first the detected information is extracted and Decoded then the priority information is used for the next iteration. From the result we can see the significance performance gain over the receiver structure from the turbo iterative structure with chip equalization.


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