6th International Young Scientist Congress (IYSC-2020) will be Postponed to 8th and 9th May 2021 Due to COVID-19. 10th International Science Congress (ISC-2020).  International E-publication: Publish Projects, Dissertation, Theses, Books, Souvenir, Conference Proceeding with ISBN.  International E-Bulletin: Information/News regarding: Academics and Research

Novel Characteristics of Junction less Dual Metal Cylindrical Surround Gate (JLDM CSG) MOSFETs

Author Affiliations

  • 1Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam 788 010, INDIA
  • 2

Res. J. Recent Sci., Volume 2, Issue (1), Pages 44-52, January,2 (2013)

Abstract

After the fabrication of a junction less (JL) transistor by the Colinge et al at Tyndall National Institute, it is now considered a substitute for the junction transistors at highly scaled dimensions. One of the biggest advantages reported is its current driving capability. Being a depletion mode device it is normally ON device and has to be switched OFF by applying a certain gate voltage. In this paper we have explored some novel characteristics of a junction less dual metal (JLDM) CSG MOSFET using 3D numerical simulations and compared it with a standard JL single metal (JLSM) transistor of identical dimensions. Some interesting properties of the JLDM has been revealed not reported earlier. Many analog and RF performance parameters of JLDM such as transconductance gm, TGF gm/TD, early voltage VEA, unit-gain cutoff frequency fT, maximum frequency of oscillation fMAX, gain bandwidth product (GBW) etc. have been observed to have improved values as compared to the JLSM.

References

  1. Shur M., Split-gate eld-effect transistor, Appl.Phys.Lett., 54(9), 162164 (1989)
  2. Saxena M., Haldar S., Gupta M., and Gupta R., Physics-based analytical modeling of potential and electrical eld distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efciency, IEEE Transactions on Electron Devices, 49(11), 19281938 (2002)
  3. Chaudhry A. and Kumar M., Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET, IEEE Transactions on Electron Devices, 51(9), 14631467 (2004)
  4. Zhou X. and Long W., A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology, IEEETransactions on Electron Devices, 45(12), 25462548 (1998)
  5. Long W., Ou H., Kuo J., and Chin K., Dual-material gate (DMG) eld effect transistor, IEEE Transactions on Electron Devices, 46(5), 865870 (1999)
  6. Long W. and Chin K., Dual material gate eld effect transistor (DMGFET), IEDM Tech. Dig., 549552 (1998)
  7. Colinge Jean-Pierre et. al, Nanowire transistors without junctions, Nature Nanotechnology, DOI: 10.1038/NNANO.2010.15 (2010)
  8. Na K. and Kim Y., Silicon complementary metal-oxidesemiconductor eld-effect transistors with dual work function gate, Jpn. J. Appl. Phys., 45(12), 90339036 (2006)
  9. Polishchuk I., Ranade P., King T., and Hu C., Dual workfunction metal gate CMOS technology using metal inter diffusion, IEEE Electron Device Lett., 22(9), 444446 (2001)
  10. Song S. et al, Highly manufacturable 45nm LSTP CMOS FETs using novel dual high-k and dual metal gate CMOS integration, VLSI Symp. Tech. Dig., 1314 (2006)
  11. Lou Haijun, Zhang Lining, Zhu Yunxi, Lin Xinnan, Yang Shengqi, He Jin, Chan Mansun, A Junctionless Nanowire Transistor with a Dual-Material Gate, IEEE Transactions on Electron Devices, 59(7), 1829-1836 (2012)
  12. Lilienfield J. E., Method and apparatus for controlling electric current, US patent 1,745,175 (1925)
  13. Lilienfield J. E., Device for controlling electric current, US patent 1,900,018 (1928)
  14. Rios R., Cappellani A., Armstrong M., Budrevich A., Gomez H., Pai R., Rahhal-orabi N., and Kuhn K., Comparison of Junctionless and Conventional Trigate Transistors With Lg Down to 26 nm, IEEE Electron Device Letters, 32(9), 1170-1172 (2011)
  15. Gundapaneni Suresh, Ganguly Swaroop, Kottantharayil Anil, Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling, IEEE Electron Device Letters, 32(3), 261-263 (2011)
  16. Su Chun-Jung, Tsai Tzu-I, Liou Yu-Ling, Lin Zer-Ming, Lin Horng-Chih, Chao Tien-Sheng, Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels, IEEE Electron Device Letters, 32(4),521-523 (2011)
  17. Singh Pushpapraj, Singh Navab, Miao Jianmin, Park Woo-Tae, Kwong Dim-Lee, Gate-All-Around Junctionless Nanowire MOSFET With Improved Low-Frequency Noise Behavior, IEEE Electron Device Letters, 32(12), 1752-1754 (2011)
  18. Chiang Te-Kuang, A Quasi-Two-Dimensional Threshold Voltage Model for Short-Channel Junctionless Double-Gate MOSFETs, IEEE Transactions on Electron Devices, 59(9),2284-2289 (2012)
  19. TCAD Sentaurus Device Users Manual, Synopsys, Mountain View, CA, (2009)
  20. Tsividis Y., Operation and Modeling of the MOS Transistor, 2nd ed. New York: Oxford Univ. Press, (1999